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Cortex X925 has a 64 KB L1 data cache with 4 cycle latency like A725 companions in GB10, but takes advantage of its larger power and area budget to make that capacity go further. It uses a more sophisticated re-reference interval prediction (RRIP) replacement policy rather than the pseudo-LRU policy used on A725. Bandwidth is higher too. Arm’s technical reference manual says the L1D has “4x128-bit read paths and 4x128-bit write paths”. Sustaining more than two stores per cycle is impossible because the core only has two store-capable AGUs. Loads can use all four AGUs, and can achieve 64B/cycle from the L1 data cache. That’s competitive against many AVX2-capable x86-64 CPUs from a few generations ago. However, more recent Intel and AMD cores can use their wider vector width and faster clocks to achieve much higher L1D bandwidth, even if they also have four AGUs.
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For the rest of filers making below $100,000 annually, the lost revenue is a mere drop in the bucket for a country currently $38.8 trillion in debt, and counting. Although IRS income breakdowns are not separately reported, we can estimate that households earning less than $100,000 a year likely pay at most $1 trillion to $1.4 trillion in federal income tax. (This number was derived on the basis of individual income taxes that raise on the order of $2.6 trillion a year. It’s important to note this group pays a large share of payroll taxes that go to funding Social Security and Medicare).